1. Field of the Present Invention
In general, the present invention relates to data processing systems, and more particularly, to methods and apparatuses that increase the load and expansion capabilities of the bus for such systems.
2. History of Related Art
Historically, personal computers have used a single bus to transfer data between different internal components of the system. These buses have been typically designed as either an Industry Standard Association (ISA) bus or an Expanded Industry Standard Association (EISA) bus. The ISA bus is a 16 bit data bus while the EISA bus is a 32 bit data bus. The bus widths and the rate at which each of these buses is capable of operating have been found limiting. Consequently, a number of attempts to increase bus speed have arisen.
One recently implemented method of increasing bus speed, is to provide an additional, so called, "local bus" which is more closely associated with the central processor then either of the above-mentioned buses, and which is capable of running at speeds that more closely approximate the speed at which the processor itself runs. Those system components which require faster operation than has been available using the slower buses (such as an output display card for an output display device) are joined to this faster or local bus. The slower EISA or ISA bus is continued in essentially unchanged form, and those components which are able to tolerate longer access times are associated therewith. Although the theory behind using a local bus is good, many local bus designs have created conflicts in accessing components thereon; which actually results in slowing the operation of the computer.
The PCI Special Interest Group (PCISIG) has designed a new local bus which may be associated in a computer system, having an Intel, PowerPC, or other processors, with other buses such as an EISA bus or ISA bus (which are hereinafter referred to broadly as standard expansion buses). This new local bus provides faster throughput of data for selected components of the system. This new bus is referred to as the "Peripheral Component Interconnect" (PCI) bus.
A computer system using this PCI bus includes in addition to the physical PCI bus a PCI host bridge circuit which controls the transfer of data among the PCI bus, the central processing unit, and main memory. The PCI host bridge circuit is arranged to control the transfer of data between the primary PCI bus and the system bus.
The PCI local bus specification, version 2.1, defines the electrical characteristics of the PCI bus. Specifically, a bus loading of 10 loads is allowed (with the assumed capacitive loading, allowed timing budget, and bus timing, definitions). Loads are calculated as follows: (1) each device that is physically soldered to the bus counts as a single load; and (2) each slot coupled to the bus counts as two loads. Conformance to the maximum loading requirements, as indicated above, results in a maximum number of four slots (8 loads) with the remaining two loads for soldered components such as a Host bridge.
It would be a distinct advantage, however, to have a method and system that would increase the maximum number of slots or soldered components that could be coupled to the bus, while conforming to the maximum loading requirements thereof. The present invention provides such a method and system.